1. Field of the Invention
The present invention relates generally to a CMOS semiconductor device and to a method of manufacturing the same, and more specifically to a CMOS semiconductor device which can effectively prevent the occurrence of latch-up phenomenon due to bipolar transistors parasitically formed when N- and P-channel MOS transistors are formed in a bulk substrate.
2. Description of the Prior Art
Recently, power consumption of a chip shows a tendency to increase with increasing integration rate of an integrated circuit. To reduce power consumption, an integrated circuit is usually formed by using CMOS circuits having low power consumption. However, in ordinary CMOS circuits having no SOI structure, there inevitably exists a PNPN junction in structure, so that parasitic thyristors are formed. Therefore, in cases where an excessive voltage due to power supply noise is applied to the input terminal of the parasitic thyristors, the thyristors are turned on and therefore an excessive current is kept passing through the device, resulting in element destruction. This phenomenon is called "latch-up".
To prevent the above-mentioned latch-up phenomenon, there have been proposed various CMOS semiconductor devices. For example, a CMOS semiconductor device has been proposed in which substrate contacts or well contacts termed a guard ring are formed so as to surround MOS transistors which configure a CMOS circuit. However, current which generates the latch-up phenomenon decreases with increasing integration rate and therefore with decreasing space between circuit elements in the CMOS semiconductor device, thus resulting in a problem in that the effect upon the prevention of the latch-up phenomenon is reduced. In addition, since some area where a guard ring is formed should be prepared when arranging circuit elements, it is difficult to realize a high integration rate.
Further, there has been proposed a CMOS semiconductor device which prevents latch-up phenomenon by using a so-called expitaxial substrate with a low parasitic resistance. In this case, the semiconductor substrate is formed with two layers in such a way that the impurity atom concentration of the surface of the semiconductor substrate on which circuit elements are formed is the same as is conventional device, but that under the substrate surface layer the atom impurity concentraction is higher than in conventional devices.
FIG. 1A shows the relationship between the holding current and voltage required to hold the latch-up phenomenon and the distance between P-channel transistor drain range and N-channel transistor drain range. The two P- and N-channel transistor drain ranges are formed in the vicinity of each other so as to form a CMOS circuit on a P-type epitaxial substrate with impurity atom concentrations of about 1.times.10.sup.18 cm.sup.-3 under the semiconductor substrate and about 2.times.10.sup.15 cm.sup.-3 in the surface layer (of about 10 .mu.m thickness). FIG. 1A clearly indicates that where an epitaxial substrate is used, both the holding current and voltage increase, so that the resistance against the latch-up phenomenon can be improved. However, the holding current and voltage are not yet sufficient in order to securely prevent the latch-up phenomenon.
Further, there has been proposed another CMOS semiconductor device for preventing the latch-up phenomenon such that a trench is provided between a well range in which one MOS transistor is formed and an epitaxial substrate in which the other MOS transistor is formed in order to electrically isolate these two ranges, that is, reduce current which turns on the parasitic thyristor.
The trench formed in the CMOS semiconductor device as described above is fairly deep to such an extent as 5 to 6 .mu.m. Further, the trench is formed near the boundary between P channel MOS transistor range and N channel MOS transistor range and then isolated electrically, in accordance with the following processes as shown in FIGS. 2(a) to 2(d):
A trench 101 with a depth of about 5 to 6 .mu.m and a width of 1.0 to 1.2 .mu.m is formed starting from an epitaxial layer 107 of low impurity atom concentration layer to a substrate 109 of high impurity atom concentration layer as shown in FIG. 2A-(a). A thin oxide film 103 is formed on the inner wall surface of the formed trench 101 as shown in FIG. 2A-(b). Thereafter, a semiconductor substance such as, for instance, silicon having a thermal expansion coefficient equivalent to that of the substrate 109 is buried within the trench 101 so as not to produce a strain in the trench 101 due to a difference in thermal expansion coefficient between the two as shown in FIG. 2A-(c). Finally, an oxide film 105 is formed on the upper surface of the trench 101 by heat treatment for electrical isolation as shown in FIG. 2A-(d).
In the prior-art process as described above, however, since the impurity atom concentration is different between the epitaxial layer 107 and the substrate 109 in the process (a), a stepped portion 113 is formed within the trench 101 due to a difference in etching speed between the two. Therefore, in the process (c) at which the tranch 101 is buried, the trench 101 is not completely buried and therefore a cavity 111 is readily produced within the trench 101. In addition, in case where a cavity 111 appears, since heat treatment for forming an oxide film 105 on the upper portion of the trench 101 is affected in the process (d), the semiconductor substance on the inner wall surface of the cavity 111 is oxidized, so that a change in volume occurs near the cavity 111 and thereby defects appear at or near the stepped portion 113.
On the other hand, it takes a long etching treatment time in order to form a relatively deep trench 101 (e.g. 5 to 6 .mu.m) in the epitaxial layer 107. Therefore, cores 112 which cause crystal defects are readily produced near the surface of the epitaxial layer 107 at which the trench 101 is formed as shown in FIG. 2B-(a). Further, in the process (d), since another heat treatment is effected to form an oxide film 105 on the upper surface of the semiconductor substance 106 buried in the trench 101, crystal defects 113 appear near the surface of the epitaxial layer 107 and around the periphery of the trench 101.
Therefore, in the case where the trench 101 is so formed as to extend from the low atom concentration layer to the high atom concentration layer to such an extent of 5 to 6 .mu.m, various deteriorations in element characteristics arise such as an increase in leakage current, a decrease in withstand voltage, a generation of interface potential level, etc., thus resulting in a problem such that production yield is lowered, as depicted in FIG. 1B.
On the other hand, as a method of suppressing the occurrence of latching phenomenon, there exists a method of forming a dielectric substance between the two complementary MOS transistars. In more detail, a trench with a width of about 1 .mu.m is formed in a substrate by RIE (reactive ion etching) technique; a 250 to 1000 A thick oxidized film is formed on the surface thereof; polycrystal silicon is buried in the trench; the polycrystal silicon is etched back by anisotropic etching method to leave the polycrystal silicon only within the trench, in order that a dielectric substance is formed between the two MOS transistors.
However, the following problems are involved in the above method: The first drawback is that the etching back technique of the trench burying material (polycrystal silicon) is not suitable for mass production processes. That is, since the buried material is thick (the film thickness almost the same as the trench width is required), the film thickness disperses and the loading effect is great in etch back process; as a result, undesired burying materials often remain disadvantageously at the periphery of the wafer.
In addition, the ordinary LOCOS (localized oxidation of silicon) cannot be adopted sometimes in the element separation process. That is, in the case where polycrystal silicon is used as the trench burying material, the polycrystal silicon is strongly oxidized by the LOCOS, so that many defects appear in the oxidized film. Further, in the case where the burying material is a CVD (chemical vapor deposition) silicon oxidized film, a stress is applied to the vertical wall surface of the trench due to the difference in thermal expansion coefficient between the two, thus causing defects.